Siew Ping Kong is a qualified expert, that works in Idt - Integrated Device Technology, Inc main office of which is in 1300. on the position of Staff Mixed-Signal Test Engineer from 2018. Siew Ping Kong gained professional experience in more than eight positions at various companies. Siew Ping Kong went to the Queen's University, Canada and was studying. San Jose, California is the city, where this expert was lastly known to be located. Siew's phone and email can be easily accessed through SoftwareOfficial by request.
Name variants:
Siew Kong
Last updated Jun 18, 2024
Contact Information
Last Update
Jun 28, 2022
Email
sp**@yahoo.com, sp**@pixelworks.com
Location
San Jose, CA
Workplace
Staff Mixed-Signal Test Engineer
San Jose, CA
Industry
Semiconductors
Colleagues
Work History
Staff Mixed-Signal Test Engineer
6024 Silver Creek Valley Rd, San Jose, CA 95138
from Nov 2018
Principal Test and Product Engineer
Mixed-signal SoC IC wafer sort test development
Test fixture design, procurement and bring up
Test plan generation; test vector conversion
System-level-test
ATE to system correlation
D...
Dec 2015 — Nov 2018
Principal Test and Product Engineer
Test fixture design, layout verification and procurement
Program development for envelop-tracking (ET) PMIC
Module/System-level bench testing
Device characterization on bench and ATE
Re...
2012 — Jul 2015
Principal Test and Product Engineer and Founder
33 north Plains Industrial Rd, Wallingford, CT 06492
New product introduction support such as device characterization, device qualification/reliability engineering
Production tester platform selection, test fixture technology evaluation, tes...
2009 — 2011
Staff Product and Test Engineer
2001 Gateway Pl SUITE 455E, San Jose, CA 95110
Supported wafer sort and chip-on-flex (COF) final test yield monitoring and improvements
Implemented test documentation using ScalarSoft DocTrac system to meet quality system requirements
...
2008 — 2009
Director, Test and Product Engineering
226 Airport Pkwy, San Jose, CA 95110
Led a team of local test/product engineers to develop test programs for low-power, high-performance logic and mixed-signal CMOS system-on-chip products
Led team of offshore (Taiwan) manufa...
2002 — 2007
Test Engineering Manager
Led a team of engineers to develop wafer sort and final test programs for xDSL AFE and processor/controller chips
Drove new product characterization, qualification, bench correlation, fail...
2000 — 2002
Staff Test Engineer
6024 Silver Creek Valley Rd, San Jose, CA 95138
Responsible for test program development for analog/ mixed-signal custom chips
Designed and procured loadboards, sockets and other needed test fixtures
Supported new product characterizat...
1994 — 1999
Occupations
Professor
School Principal
Engineer
Sales Specialist
Supplier
Pilot
School Administrator
Educational Manager
Services Professional
Sales Representative
Air Transportation Worker
Skills
Mixed Signal
Ic
Analog
Testing
Failure Analysis
Cmos
Soc
Test Engineering
Cross Functional Team Leadership
Dft
Product Engineering
Characterization
Spc
Manufacturing
Semiconductors
Product Engin
Contract Manufacturing
Yield Management