Since 2015, Eric Chang Hong has been working in Esilicon located 1300, 1300. This professional is a proficient Principal Design Engineer with over 25 years of work experience. According to Eric's resume and work profile, this person has worked at more than nine companies with diverse backgrounds and got various skills. Eric attended school at the Stanford University from 1994 to 1997. Eric Chang Hong can be found in San Francisco, California – where this professional currently lives. You can search for Eric Chang Hong's email address and phone. We can also provide you exhaustive contact information upon request.
Name variants:
Erik Hong,
Erick Hong,
Rick Hong,
Ricky Hong
Last updated May 12, 2024
Contact Information
Workplace
Colleagues
Work History
Principal Design Engineer
2130 Gold St SUITE 100, San Jose, CA
Analog-mixed signal IP development
May 2015 — Jun 2018
Senior Director of Engineering
97 east Brokaw Rd #250, San Jose, CA 95112
Leading the development of high-speed, high-performance, low-power Interface IPs such as PHY, SerDes, Transceivers and PLLs.
from Jun 2018
Senior Director of Engineering
ASIC/Analog design for sensor application ADC IP development
Oct 2013 — Apr 2015
Principal Engineer
2701 San Tomas Expy, Santa Clara, CA 95050
PLL/DLL and Clock distribution design
H1/HT3, DP, HDMI, PCI-E Gen3/Gen2, DDR3, GDDR5 PHY development
Voltage regulator design for PLL/DLL and IO circuits.
Jan 2004 — May 2013
Design Manager
Was in charge of all circuit and signal integrity related activities. FA analysis and chip bring-up and ESD design.
SPI, DDR and ZBT SSRAM interface design and system level timing analysis...
Dec 2000 — Dec 2003
Design Manager
800 west 6Th St, Austin, TX 78701
Managed a team of engineers developing mixed-signal IPs.
PLL and USB transceiver design
SRAM, ROM and high-speed datapath development
ESD and IO library developement
Aug 1999 — Jun 2001
Project Manager
Project leader for developing single and dual port SRAM compiler, 2P register file compilers.
Developed innovative redundancy implementation and fuse macro
Collaborated on BIST implementa...
May 1998 — Sep 1999
Design Engineer
Charge pumps(voltage booster) design for flash memory
Flash, EEPROM, CPLD and SRAM circuit design
CPU supervisory circuit design with battery switch. POR, untra-low power oscillator, VCC ...
Jul 1995 — May 1998
Design Engineer
Santa Clara, CA
Designed readpath circuits for Flash memory
Worked on FA, reliability, yield enhancement, chip bring-up and characterization
Worked on full-chip timing analysis
Dec 1993 — Sep 1995
Education
Occupations
Executive
Senior Director
Engineer
Project Engineer
Professor
School Principal
Senior Manager
Operations Manager
Engineering Specialist
School Administrator
Educational Manager
Skills
Signal Integrity
Serdes
Processors
Static Timing Analysis
Asic
Mixed Signal
Usb
Ic
Pcie
Spi
Timing Closure
Flash Memory
Ddr