Yolin Lih is a high-level expert, who works in Risclouds as a Consulting Chief Archiect and Program Manager from 2018. Yolin Lih gained professional experience in more than 14 positions at different companies. Yolin Lih went to the Stanford University and received education there from 1994 to 1999. San Francisco, California is the city, where this professional was lastly known to be situated. Yolin Lih's email address and number can be easily accessed through SoftwareOfficial on demand.
Name variants:
Yolin Lih
Last updated Jun 12, 2024
Contact Information
Last Update
Jul 6, 2022
Email
yo**@gmail.com, yo**@huawei.com, yo**@gmail.com
Location
San Francisco, CA
Company
Risclouds
Workplace
Consulting Chief Archiect and Program Manager
Work History
Consulting Chief Archiect and Program Manager
This is pre-startup technical group, targeting to deliver RISC-V CPU, multi-core cluster, cache & memory subsystem, and large scale interconnect.
from Dec 2018
Senior Manger, System Archiect
1524 Logan Ave, Salt Lake City, UT 84105
Defining the system level usage and architecture for the emerging memory technology. Focusing on the memory subsystem in the mobile and AI/DL/ML friendly environments, to replace DRAM with t...
from Nov 2017
Archiect Expert
In the time reverse order:
Architect, design lead, and program manager, multi-thread ARM V8 CPU.
Architect, design lead, and program manager, L1$, L2$, L3$ and multi-core cluster
Archite...
Jun 2011 — Nov 2017
Senior Manager, Emergent Memory System Architect
8000 south Federal Way, Boise, ID 83716
Defining the system architecture for emergent memory technologies， emphasizing the memory subsystem for 5G mobile and AI/ML。
from Nov 2017
Principle Architect, Project Manager
Define the architecture of CPU, DSP, cache memory subsystem, network processing systems, and proprietary but company wide cache coherency and memory consistency interconnect protocols. Techn...
Jun 2011 — Oct 2017
Spacetime Fpga Memory Tile Lead
3250 Olcott St, Santa Clara, CA 95054
Memory and circuit designer and lead: memory tiles in the Space-Time FPGA, a Dynamic Programmable Logic Array.
Apr 2008 — Jun 2011
Cache Memory Design Lead
Montalvo was building a extremely low power dual-core X86 chip with an asymmetrical architecture. Instead of working on the architecture area, I decided to put efforts on the SRAM to overcom...
Nov 2005 — Apr 2008
Technical Lead
5301 Stevens Creek Blvd, Santa Clara, CA 95051
Redswitch was a spin-off from Hal Computer (year 2000), and was acquired by Agilent in year 2004. Redswitch was building the switch and channel adapter for both Infiniband and Rapid-IO. -- I...
May 1, 2000 — Aug 1, 2004
Architect and Design Lead of Infiniteband Chip Set and Rapid Io Chip Set
Infiniteband (IB) chip set: architect and design lead of IB PHY, LINK, IB port module, and Subnet Manager. -- Rapid IO chip set: architect of RIO port module.
Jul 2000 — Aug 2004
Chief Hardware, Alpha Cpu
3000 Hanover St, San Jose, CA
Logic and Circuit design lead of Memory Box and Xbar box for Alpha 7 CPU.
Feb 2000 — Jun 2000
Seniro Memory of Techbical Staff
1501 Page Mill Rd, Palo Alto, CA 94304
In time reverse order: -- Logic and VLSI design, CC-NUMA Core-Exclusive chip set for N-class enterprise computing system. -- RTL and VLSI reference design for HP Wide Word PA-RISC.
Jan 1993 — Jan 2000
Mts
3000 Hanover St, San Jose, CA
I was a member in the following project:
HP PA Wide Word RISC:
Responsible for the instruction unit micro architecture and RTL.
HP N-class enterprise computing server chip set:
Responsi...
Jan 1993 — Jan 2000
Senior Memory of Technical Staff
San Jose, CA
Technical lead for Sparc V9 64-bit Super Scaler CPU & MMU:
I have designed the following functional units:
TLB and L1 cache memory
May 1991 — Jan 1993
Senior Manager, Specialty Memory Group
I am the manager and the design lead of the DSP and Specialty Memory IC design group.
The DSP and specialty memory. I have:
Developed the DSP algorithms & architecture for a family of sou...
Feb 1987 — May 1991
Education
1994 — 1999
1978 — 1980
1978 — 1980
1975 — 1978
Occupations
Executive
Program Director
Operations Manager
Skills
Fpga
Processors
Arm
Digital Signal Processors
Testing
Architecture
Integrated Circuit Design
Soc
Verilog
Low Power Design
Computer Architecture
Integrated Circuits
Field Programmable Gate Arrays
Application Specific Integrated Circuits
Semiconductors
Rtl Design
Cmos
Debugging