Wael Khansa is a high-level expert, that works in Intel Corporation main office of which is in 1286. on the position of Senior Wireless Rtl Design Engineer from 2016. Wael gained professional experience in more than 11 positions at various companies. Wael Khansa went to the University of North Carolina at Charlotte and received education from 1995 to 1997. Santa Clara, California is the area, where the professional was known to live. This person's email address and number can be accessed through SoftwareOfficial on demand.
Name variants:
Wael Khansa
Last updated Jun 15, 2024
Contact Information
Last Update
Jul 10, 2022
Email
wa**@intel.com, wa**@yahoo.com, wa**@nokia.com
Location
Santa Clara, CA
Company
Workplace
Colleagues
Work History
Senior Wireless Rtl Design Engineer
Santa Clara, CA
Senior Wireless RTL Design Engineer at Intel Corporation
from Mar 2016
R and D Digital Hardware and Fpga Engineer
Working as part of a focused product development engineering team responsible for the design, development, test, and support of Wireless Infrastructure architectures and products. RTL code d...
Jul 2013 — Mar 2016
Staff Fpga Applications Engineer
5555 northeast Moore Ct, Hillsboro, OR 97124
Provided pre-sales and post-sales customer technical support of FPGA devices. Maintained cross-functional cooperation with R&D, technical marketing, and field sales. Wrote software usage mod...
Jul 2001 — Dec 2012
Application Specific Integrated Circuit -ASIC- Designer
Allentown/Bethlehem/Easton, PA
Jul 1997 — Jul 2001
Asic Designer
Implemented critical aspects of the ASIC design flow from RTL HDL design to chip testing. Took project ownership and directed the activities of physical design and test engineers.
Jun 1997 — Jul 2001
Education
Masters of Science in Electrical Engineering
Charlotte, NC
1995 — 1997
1990 — 1994
Occupations
Engineer
Project Engineer
Engineering Specialist
Skills
Fpga
Asic
Debugging
Rtl Design
Simulations
Verilog
Vhdl
Static Timing Analysis
Serdes
Modelsim
Integrated Circuit Design
Rtl Coding
Vlsi
Dft
Circuit Design
Microprocessors
Cpld
Rtl
Floorplanning
Active Hdl
Synplify Pro
Synthesis
Board Debug
Drc
Spice
Physical Verification
Xilinx Ise
Lattice Semiconductor Isplever/Diamond
Embedded Software Programming
Documentation
Logic Analyzer
Altera Quartus
Altera
FPGA Applications Enginnering
VHDL/Verilog Design
behavioral testbenches
RTL/Timing Simulations
RTL synthesis
Static Timing Analysis
ASIC and FPGA implementation flows
Hardware debugging skills
fast/GbE/10GBE Ethernet PCS/MAC experience