Tom Karabinas

Asic Design For Test Engineering Leader

Tom Karabinas is a high-level expert, working in Cisco main office of which is in 1300. on the position of Asic Design For Test Engineering Leader from 2017. This person has earned professional experience in more than seven positions at different companies. Tom Karabinas went to the The Ohio State University and got education from 1981 to 1986. This professional has professional qualifications: Data Visualization: Storytelling, Learning Data Science: Understanding the Basics, and Data Science Tools of the Trade: First Steps. San Bernardino, California is the area, where this expert was known to live. The person's email address and phone can be easily accessed through SoftwareOfficial on demand.
Name variants:
Thomas Karabinas
Last updated Jun 16, 2024

Contact Information

Last Update
Jun 22, 2022
Email
to**@gmail.com, to**@oracle.com, to**@gmail.com
Location
San Bernardino, CA
Company

Workplace

Cisco
Asic Design For Test Engineering Leader

San Jose, CA

Industry

Computer Networking

Work History

Asic Design For Test Engineering Leader

San Jose, CA
from May 2017

Director Hardware Engineering

500 Oracle Pkwy, California
With more than 380,000 customers—including 100 of the Fortune 100—and with deployments across a wide variety of industries in more than 145 countries around the globe, Oracle offers an optim...
Jan 1998 — Mar 2017

Engineering Manager

1996 — 1998

Senior Engineer

Jan 1994 — Sep 1994

Senior Engineer

1991 — Jan 1994

Senior Engineer

Santa Clara, CA
1989 — 1991

Design Engineer

Sep 1986 — Sep 1989

Occupations

Leader
IT Professional
Computer Network Consultant
Executive
Director
Managers
Computer Consultant
IT Consultant
Operations Manager

Skills

Engineering Management
Processors
Asic
Soc
Rtl Design
Functional Verification
Microarchitecture
Dft
Hardware Architecture
Silicon Debug
Computer Architecture
Hardware Design
Microprocessors
Silicon Validation
Semiconductors
Debugging
Hardware
Fpga
Pcie
System Architecture
Embedded Systems
Verilog
Eda
Ic
Vhdl
Physical Design
Vlsi
Static Timing Analysis
Systemverilog
Logic Design
Simulations
Rtl Coding
High Performance Computing
Field Programmable Gate Arrays
Very Large Scale Integration
Integrated Circuits
System on A Chip
Application Specific Integrated Circuits
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