Name variants:
Thomas Jose
Last updated Jun 22, 2024
Contact Information
Workplace
Colleagues
Work History
Design Engineer at Tactual Labs Co
New York, NY
RTL Design, Verification, Validation, ASIC prototyping on FPGA
Jun 2015 — Feb 2019
Graduate Student
2600 Clifton Ave, Cincinnati, OH 45202
Aug 2014 — May 2015
Senior Design Engineer
FPGA based RTL design, verification and on board validation
Completed more than 10 projects from specification to final release
Micro and Macro architecture design
RTL equivalent Matlab ...
Sep 2009 — Jul 2014
Education
2014 — 2015
2005 — 2009
1991 — 2005
Occupations
Engineer
Project Engineer
Engineering Specialist
Skills
Verilog
Vlsi
Fpga
Modelsim
Vhdl
Rtl Design
C
Simulations
Integrated Circuit Design
Functional Verification
C++
Matlab
Xilinx
Rtl Coding
Validation
Digital Signal Processors
Systemverilog
Embedded Systems
Static Timing Analysis
Asic/Fpga Design
Hardware Verification
Eda
Tcl
Synopsys Tools
Debugging
Altera Quartus
Electrical Engineering
Pcie
Ddr2
Ddr3
Xilinx Ise
Perl
Synopsys Primetime
Bist
Dft
Dft Compiler
Spice
Algorithms
Logic Synthesis
I2C
Asic
Spi
Hardware Architecture