Sunkavalli Ravi
Senior Director, Acceleration Solutions, Cloud Platform and Technician Group, Dcg
Sunkavalli Ravi is a high-skilled professional, working in Intel Corporation main office of which is in 1286. on the position of Senior Director, Acceleration Solutions, Cloud Platform and Technician Group, Dcg from 2019. Sunkavalli has earned professional experience in more than eight positions at different companies. Sunkavalli Ravi went to the Indian Institute of Management Bangalore and received education from 2009 to 2009. San Francisco, California is the area, where this expert was known to live. Their e-mail and phone can be accessed through SoftwareOfficial on demand.
Name variants:
Sunkavalli Ravi
Last updated Sep 18, 2024
Contact Information
Workplace
Senior Director, Acceleration Solutions, Cloud Platform and Technician Group, Dcg
Santa Clara, CA
Industry
Semiconductors
Colleagues
Work History
Senior Director, Acceleration Solutions, Cloud Platform and Technician Group, Dcg
Santa Clara, CA
from Jul 2019
Senior Director, Ip Engineering
2100 Logic Dr, San Jose, CA 95124
Worked closely with all major hyperscale and key customers to initiate and lead Xilinx Datacenter acceleration solutions leveraging FPGAs for compute, networking, storage workload & infrastr...
2012 — Jul 2019
Vice President Product Development
1250 Borregas Ave, Sunnyvale, CA 94089
Engaged with partners to develop new memory products and system level IP leveraging CBRAM technology. Granted 5 patent applications related to system level architectural improvements enabled...
2011 — 2012
V.p., Hardware Engineering
2903 Bunker Hill Ln, Santa Clara, CA 95054
Built the hardware team, architected and successfully delivered the first 65nm GHz FPGA product at Achronix.
Started and managed the Achronix Bangalore design center to scale up hardware a...
2006 — 2011
Director, Ic Design
Lead for all IC design activity and FPGA co-architect.
Responsible for FPGA design, implementation, packaging and test.
Managed successful tape-out a 500MHz, 90nm FPGA in 2006 demonstrati...
2003 — 2006
Manager
Technical Lead for SRAM architecture definition and feasibility for 0.13um and 90nm including foundry interface. Manage design and validation of all new testchips across all foundries.
2002 — 2003
Mts, K8 Design
2485 Augustine Dr, Santa Clara, CA 95054
Worked on library design and L2 cache circuit design for first x86-64bit processor (K8/Opteron).
2000 — 2002
Mts, Flash Technology Development
2485 Augustine Dr, Santa Clara, CA 95054
Flash transistor and device engineering for multiple generations (0.35um, 0.25um, 0.18um) of floating-gate NOR and charge-trapping mirror-bit NOR flash. More than 20 granted patents.
1996 — 2000
Education
2009 — 2009
1994 — 1996
1992 — 1994
1988 — 1992
Occupations
Executive
Senior Director
Technician
Security
Doctor of Musical Arts
Senior Manager
Operations Manager
Technical Specialist
Technical Support Specialists
Skills
Asic
Semiconductors
Microprocessors
Physical Design
Integrated Circuit Design
Ic
Fpga
Mixed Signal
Soc
Vlsi
Verilog
Field Programmable Gate Arrays
Application Specific Integrated Circuits
System on A Chip