Simon Curry is a skilled professional, that works in Sequitur Labs as a Director Software Architecture since 2011. This expert has earned professional experience in more than 15 positions at various companies. Simon Curry went to the University of Essex and was studying from 2017 to 2018. Boston, Massachusetts is the area, where this professional was lastly known to be situated. Simon's phone and email are accessed through SoftwareOfficial by request.
Name variants:
Si Curry,
Sy Curry,
Sim Curry,
Simie Curry,
Simmy Curry
Last updated Jun 18, 2024
Contact Information
Last Update
Jan 29, 2016
Email
si**@comcast.net
Location
Boston, MA
Company
Sequitur Labs
Workplace
Director Software Architecture
Work History
Director Software Architecture
Shared responsibility for Sequitur Policy Administration Framework architecture
Responsibility for Policy Administration Framework Language Design
Responsibility for Policy Language compi...
from Jan 2011
Director Software Architecture
33404 southeast Redmond Fall, Fall City, WA
Shared responsibility for Sequitur Policy Administration Framework architecture
Responsibility for Policy Administration Framework Language Design
Responsibility for Policy Language compi...
from Jan 2011
Senior Staff Engineer
Functional Verification for wireless communications chips
CSM (8700) and MDM chip verification
802.11n (MAC & PHY), SRIO, CDMA
Infrastructure development
System Verilog, OVM, System...
Sep 2006 — Jan 2011
Senior Staff Engineer
San Diego, CA
Functional Verification for wireless communications chips
CSM (8700) and MDM chip verification
802.11n (MAC & PHY), SRIO, CDMA
Infrastructure development
System Verilog, OVM, SystemC (T...
Sep 2006 — Jan 2011
Verification Specialist
Verification Architect (contractor) at Qualcomm Inc., Concord Mass. IEEE 802.11n; System Verilog, SystemC
Multi-platform System Verilog model for multi-station wireless network
Verificati...
Dec 2005 — Sep 2006
Verification Specialist
Verification Architect (contractor) at Qualcomm Inc., Concord Mass. IEEE 802.11n; System Verilog, SystemC
Multi-platform System Verilog model for multi-station wireless network
Verificatio...
Dec 2005 — Sep 2006
Ic Design Staff Principal
6501 William Cannon Dr west, Austin, TX 78735
System level modeling 10G NPU (SystemC, C++) Verification Lead: Dual-Processor platform SOC (Vera, Perl,Verilog)
Oct 2002 — Dec 2005
Principal Verification Engineer
Member of verification team for next generation fabric chip set for Avici worm-hole router. (Vera, PERL, C++)
2001 — 2002
Principal Hardware Engineer
Verification lead for 10G NPU (RSPII) [Verilog, C++, PERL]
Control-Plane/Data-Plane data transformation + fastpath code for Vitesse/Sitera IQ2000 NPU [Assembler, C, C++, TCL, PERL]
1998 — 2001
Principal Hardware Engineer
Verification lead for 10G NPU (RSPII) [Verilog, C++, PERL]
Control-Plane/Data-Plane data transformation + fastpath code for Vitesse/Sitera IQ2000 NPU [Assembler, C, C++, TCL, PERL]
1998 — 2001
Senior Engineering Manager, Architect
2655 Seely Ave, San Jose, CA 95134
Senior Engineering Mgr: CAD tools
Architect: Sys.Level Design Verification tools
Verification Architect/Lead: Cadence Design Services, Rochester NY.
1993 — 1998
Manager, System Level Modeling
Manager and team lead: B.N.R System-Level modeling and VHDL tool development team.
1987 — 1993
Vice President R and D
LISP-based silicon compilation tools; graphics/animation chip design
1983 — 1986
Professor
One of the three founding professors of Computer Science at UQAM, in the Department of Mathematics and Computer Science.
Active in building B.Sc., M.Sc., and Ph.D. programs
Teaching speciali...
Aug 1971 — Jun 1989
Professor
One of the three founding professors of Computer Science at UQAM, in the Department of Mathematics and Computer Science.
Active in building B.Sc., M.Sc., and Ph.D. programs
Teaching speci...
Aug 1971 — Jun 1989
Education
2017 — 2018
1967 — 1970
1964 — 1967
1959 — 1964
1959 — 1964
Occupations
Executive
Director
Security
Engineer
Staff Engineer
Military
Command Sergeant Major
Counselor
Operations Manager
Professional Engineer
Engineering Specialist
Advisor
Skills
SystemVerilog
Verilog
TCL
SystemC
VHDL
Perl
Open Verification Methodology
Vera
C++
Python
Scripting
Assembler
Lisp
Ruby
ASIC
HVL
SoC
Functional Verification
Formal Verification
RTL design
EDA
Simulations
Integrated Circuit Design
Silicon
Embedded Systems
Computer Architecture
Systemverilog
Tcl
Systemc
Vhdl
Asic
Hvl
Soc
Rtl Design
Eda
Logic Synthesis
Cadence
Algorithms
Compilers
Ic
Fpga
Software Engineering
Debugging
System on A Chip
Software Development