Seng Oon Toh is a eficient professional, working in Linus Health as a Chief Technology Officer and Co-Founder from 2019. This person gained professional experience in more than ten positions at different companies. Seng Oon Toh went to the University of California, Berkeley and received education there from 2005 to 2011. Riverside, California is the area, where this expert was lastly known to settle. This professional's phone number and email can be accessed through SoftwareOfficial by request.
Name variants:
Seng Toh
Last updated Jun 15, 2024
Contact Information
Last Update
Jul 13, 2022
Email
se**@gmail.com
Location
Riverside, CA
Company
Linus Health
Workplace
Chief Technology Officer and Co-Founder
Work History
Low Power Wireless Ip Implementation Lead
Low power Bluetooth 5.0 digital implementation NB-IOT testchip design and implementation
Jan 1, 2016 — Oct 2018
Advisor
1 Venture, Irvine, CA 92618
TMC Group is a private holding company with real estate and financial investments in the U.S. and Asia. The Group has made over 100 private equity and venture capital investments during the ...
from Aug 2016
Venture Partner
301 east 8Th St, New York, NY 10009
Tamarisc is an early stage venture capital firm. We invest in real estate technology companies that improve how we live, work and travel within the built environment. www.tamarisc.com
from Aug 2016
Co Founder and Chief Technology Officer
Irvine, CA
Helping families get more sleep. At Huckleberry Labs, we start with the understanding that every child is unique, and every family is unique. By understanding your child’s specific sleep pat...
from Aug 2016
Staff Implementation Engineer
Implementation lead of a CPU design.
Minimum energy wireless sensor node design.
Developed Cortex-A53 Synopsys reference implementation.
Refined EDA flows for live-slave retention power ...
Aug 2013 — Jan 2016
Senior Design Engineer
2485 Augustine Dr, Santa Clara, CA 95054
Implemented adaptive voltage and frequency scaling capability on Carizzo APU.
Low-power advanced development of CPU and GPU.
Process technology optimization for 20nm Accelerated Processin...
Mar 2011 — Aug 2013
Graduate Student Researcher
Berkeley, CA
Developed a convex optimization framework for power‐performance optimization of synthesized integrated circuits, which enables better circuit design for low power, high performance, and mult...
2005 — 2011
Co-Op Engineer at Amd Research
2485 Augustine Dr, Santa Clara, CA 95054
Designed and taped out L1 SRAM array characterization test structure in an advanced technology node.
Jan 2010 — May 2010
Intern
Reduced power consumption of a multimedia processor by 30% through optimal process technology and architecture optimization.
May 2007 — Aug 2007
Education
2005 — 2011
1999 — 2002
Occupations
Executive
Technology Director
Co-Founder
Health Specialist
Wellness and Fitness
Technology Manager
Technical Managers
Founder
Chief Executive
Skills
Ic
Circuit Design
Eda
Cadence Virtuoso
Semiconductors
Physical Design
Low Power Design
Verilog
Cmos
Spice
Asic
Processors
Analog Circuit Design
Vlsi
Circuit Device Co Design
Physical Design In Advanced Technology Nodes
Power Performance Optimization
Synopsys Design Compiler
Synopsys Ic Compiler
Cadence Genus Synthesis
Cadence Innovus
Apache Spark
Integrated Circuits
Very Large Scale Integration
Arm Architecture
Application Specific Integrated Circuits
System on A Chip
Matlab