Sen Chu is a qualified professional, that works in Global Communication Semiconductors,Inc main office of which is in 117. as a Cad Tape-Out Engineer since 2016. Sen has earned professional experience in more than six positions at different companies. Sen Chu went to the University of Southern California and got education from 1979 to 1983. Los Angeles, California is the area, where this expert was known to live. This expert's phone number and email can be easily accessed through this website by request.
Name variants:
Sen Chu
Last updated Aug 27, 2024
Contact Information
Last Update
Aug 1, 2022
Email
se**@skyworksinc.com
Location
Los Angeles, CA
Workplace
Cad Tape-Out Engineer
Torrance, CA
Industry
Semiconductors, Mfg Semiconductors/Related Devices, Whol Electronic Parts/Equipment, Semiconductor Manufacturer, Electronic Parts and Equipment, NEC
Colleagues
Work History
Cad Tape-Out Engineer
23155 Kashiwa Ct, Torrance, CA 90505
Layout of wafer masksets for Opto/HBT/GaN/PHEMPT process
Nov 2016 — Jun 2017
Mixed Signal Design and Fa Egineer
5221 California Ave, Irvine, CA 92617
Perform failure analysis of IC chips containing both BiFET and CMOS dice to identify the cause of the failure and to generate the report.
2014 — 2015
Staff Design Engineer
5488 Marvell Ln, Santa Clara, CA 95054
Mixed Signal IC Chip Designer responsible for the development/support of the following IP sub-blocks intended for TSMC 90nm/60nm/28nM/20nm CMOS process. LVDS transceivers with low EMI requir...
Nov 2006 — Jan 2014
Senior Rfic Design and Layout Engineer
Design/develop chip-level ESD protection scheme and ESD structures for RFIC products. Design/develop families of I/O cells, standard logic cells, and IP sub-blocks for RFIC products.
Aug 2005 — Mar 2006
Senior Staff Design Engineer
Camarillo, CA
Design, develop, validate, and support high performance I/O and Core-Logic cells used by VTSS 0.13M CMOS products. Design and develop a standard chip-level ESD scheme and ESD review procedu...
Jun 1998 — Mar 2005
Staff Engineer
Waltham, MA
Principal person for the development of libraries of metal programmable Bipolar CML standard cells suitable for building digital Pipeline Signal Processing (PSP) elements such as adders, mul...
Mar 1983 — Aug 1998
Education
1979 — 1983
Occupations
Engineer
Electrical Engineer
Skills
High Speed Interfaces
Mixed Signal Ic Design
Esd Control
Cadence Schematic Capture
Cadence Virtuoso Layout Editor
P Spice
Spice
Functional Verification
Power Management
Standard Cell
Cmos
Gaas
Sige
Bicmos
Ic
Mixed Signal
Asic
Vlsi
Simulations
Serdes
Physical Verification
Failure Analysis
Signal Processing
Characterization