Satish Kadaba is a high-skilled expert, who works in Oracle as a Senior Engineer Pre-Silicon Verification from 2010. Satish gained professional experience in more than five positions at different companies. Satish Kadaba went to the San Jose State University and was studying from 1997 to 1999. This person has such professional qualifications as Professional Engineer - Ca, Electrical. Sunnyvale, California is the area, where this person was known to live. Satish Kadaba's email address and phone are easily accessed through SoftwareOfficial by request.
Name variants:
Satish Kadaba
Last updated Jun 09, 2024
Contact Information
Workplace
Senior Engineer Pre-Silicon Verification
Redwood City, CA
Industry
Information Technology and Services
Colleagues
Work History
Senior Engineer Pre-Silicon Verification
500 Oracle Pkwy, California
Complete ownership of design verification infrastructure development using SystemVerilog UVM/VMM including DFT features validation of SOC design developed at Oracle. SOC IP integration using...
2010 — 2017
Senior Engineer Pre-Silicon Verification
3401 Hillview Ave, Palo Alto, CA 94304
Implementation and verification of DFT features for ASIC's and SOC designs using Verilog RTL with LogicBIST and JTAG architecture designed for workstations and graphics systems.
Used Clear...
1997 — 2010
Simulation and Dft Engineer
850 east Arapaho Rd SUITE 270, Richardson, TX 75081
Worked as a corporate support simulation / DFT engineer to qualify CMOS technology library cells which are provided as design kits to all locations of VLSI Technology design centers. Qualifi...
1992 — 1997
Project Engineer
Designed, developed and tested electronic (analog and digital circuits) prototype products for 3-phase six step solar photo voltaic water pump project involving DC-A/C inverter (thyristor / ...
1984 — 1986
Education
1997 — 1999
Occupations
Technical Specialist
Engineer
Senior Design Engineer
IT Professional
Unix Administrator
Technical Support Specialists
Head Engineer
Engineering Manager
Systems Administrator
Computer Systems Administrator
Skills
Verilog
Design For Test Validation
Systemverilog
Dft
Verification and Validation
Universal Verification Methodology
Debugging
Perl
Software Development
System on A Chip
Engineers
Project Implementation
Design
Firmware
Application Specific Integrated Circuits