Rod Mcinnis is a highly qualified professional, that works in Nvidia main office of which is in 1286. on the position of Senior Design Engineer since 2013. This expert gained professional experience in more than 12 positions at different companies. Rod Mcinnis went to the California State University, Fullerton and was studying there from 1976 to 1980. Milpitas, California is the area, where this expert was lastly known to live. Their contacts can be easily accessed through SoftwareOfficial by request.
Name variants:
Roderic Mcinnis,
Rodney Mcinnis,
Rodrigo Mcinnis,
Roger Mcinnis
Last updated Jun 16, 2024
Contact Information
Last Update
Jul 14, 2022
Email
ro**@ariradesign.com, rm**@sbcglobal.net
Location
Milpitas, CA
Company
Workplace
Senior Design Engineer
Santa Clara, CA
Industry
Computer Hardware, Mfg Semiconductors/Related Devices & Custom Computer Programming, Mfg Semiconductors/Related Devices and Custom Computer Programming, Radio and Television Broadcasting and Wireless Communication, Semiconductor and Related Device Manufacturing, Custom Computer Programming Svcs, Semiconductor Devices (Manufac
Colleagues
Work History
Design Engineer
2001 Gateway Pl SUITE 500W, San Jose, CA 95110
FPGA and Board Level design
from 2015
Senior Design Engineer
48720 Kato Rd, Fremont, CA 94538
Sr. Design Engineer
RTL design
FPGA Emulation
Lead engineer on two ASIC developments
Aug 2008 — Apr 2012
Senior Hardware Design Engineer
1320 Ridder Park Dr, San Jose, CA 95131
Feb 2006 — Jun 2007
Senior Hardware Design Engineer
Significant contributor to the design, development, debug and verification of two major ASICs used for Ethernet Routing / VOIP. "last engineer standing" as company sold assets, IP and went o...
May 2002 — Aug 2004
Senior Hardware Design Engineer
2160 Gold St, San Jose, CA
Major contributor to three ASIC designs, Co-inventor on U.S. Patent #6,233,389 "Multimedia time warping system"
Oct 1997 — May 2002
Asic Design Engineer
1320 Ridder Park Dr, San Jose, CA 95131
ASIC design engineer working on an integrated, single chip system intended for “internet appliance” applications. Co-inventor on US patent 6,247,084 " Integrated circuit with unified memory ...
Dec 1996 — Oct 1997
Hardware Design Engineer
345 Park Ave, San Jose, CA 95110
Hardware design engineer, developing printer controllers (raster image processors).
Feb 1992 — Dec 1996
Education
Occupations
Engineer
Project Engineer
Senior Design Engineer
Engineering Specialist
Head Engineer
Engineering Manager
Skills
Asic
Fpga
Rtl Design
Debugging
Ethernet
Semiconductors
Processors