Poonacha Kongetira is a high-level expert, that works in Google main office of which is in 1075. on the position of Chips from 2017. Poonacha Kongetira has earned professional experience in more than seven positions at different companies. Poonacha Kongetira went to the Purdue University and received education there from 1992 to 1994. San Francisco, California is the area, where the professional was lastly known to be living. The professional's email address and number are easily accessed through this website by request.
Name variants:
Poonacha Kongetira
Last updated May 20, 2024
Contact Information
Last Update
Jul 9, 2022
Email
p.**@avogy.com, ko**@yahoo.com
Location
San Francisco, CA
Company
Workplace
Colleagues
Work History
Vice President Systems Engineering
677 River Oaks Pkwy, San Jose, CA 95134
➢ Owned electrical, mechanical & FW engineering for Zolt power supplies. This included board design and manufacturing, EMI and safety compliance, thermal design for user comfort and reliabil...
Mar 2015 — Dec 2016
Vice President Engineering
2870 Zanker Rd SUITE 210, San Jose, CA 95134
Defined and managed the architecture, implementation and productization of a platform for NoC interconnect synthesis, implementing AXI, AHB, APB protocols with support for power management. ...
Aug 2013 — Jan 2015
Senior Director Hardware Engineering
2701 San Tomas Expy, Santa Clara, CA 95050
Site Leader for Bangalore, ran engineering centre of over 700 people.
Built a GPU engineering team in Bangalore of 300, drove first GPU bringup, started new tester lab.
Directly managed p...
May 2007 — Jul 2013
Director Hardware Engineering
3401 Hillview Ave, Palo Alto, CA 94304
Director for the third generation Niagara CPU program at Sun (2004-2006).
Handled product definition, worked with architects to analyze design choices on perf/power/TCO at the rack level. ...
Jul 2002 — Aug 2006
Director of Vlsi
The multi-threaded chip architecture developed at Afara became the UltraSparc-T1(Niagara) processor after acquisition by Sun.
Managed micro-architecture, rtl, verification and timing for t...
Jan 2001 — Jul 2002
Various
3401 Hillview Ave, Palo Alto, CA 94304
Hardware Manager, technical lead, UltraSparc-V, managed Instruction Scheduling unit, contributed to architecture and circuits for Renaming logic, Memory Disambiguation logic
UltraSparc-IIi...
Nov 1994 — Dec 2000
Education
1992 — 1994
1982 — 1988
Occupations
Executive
Vice President
Sales Specialist
Equipment Tools Purchasing Agent
Supplier
Chief Executive
Department Store Salesperson
Retail Salesperson
Services Professional
Sales Representative
Skills
Soc
Processors
Debugging
Semiconductors
Ic
Eda
Embedded Systems
Verilog
Asic
Hardware Architecture
Semiconductor Ip
Graphics Processing Unit
Pcb Design
Project Management
Product Development
Vendor Management
Customer Engagement
Manufacturing Operations Management
Chipset