Peter Smeys is a skilled expert, who works in Invensense, Inc main office of which is in 1300. as a Senior Director, Foundry Technology Development and Manufacturing since 2014. This expert has earned professional experience in more than nine positions at various companies. Peter Smeys went to the Stanford University and was studying there. San Jose, California is the area, where this professional was lastly known to settle. Peter Smeys's email address and phone number can be accessed through SoftwareOfficial on demand.
Name variants:
Petr Smeys,
Pete Smeys,
Petie Smeys,
Petey Smeys
Last updated Apr 30, 2024
Contact Information
Last Update
Jul 11, 2022
Email
sm**@yahoo.com, ps**@invensense.com
Location
San Jose, CA
Company
Workplace
Senior Director, Foundry Technology Development and Manufacturing
San Jose, CA
Industry
Semiconductors, Mfg Micro-Electro-Mechanical Systems Gyroscopes, Mfg Semiconductors/Related Devices
Colleagues
Work History
Senior Director, Foundry Technology Development and Manufacturing
1745 Technology Dr #200, San Jose, CA 95110
Manages foundry relationships
Drives foundry mems and cmos process development strategy
Manages process development activities and transfers
Manages production yield engineering and cont...
Mar 2014 — Jan 2017
Director, Nanotechnology and Mems Development
12500 T I Blvd, Dallas, TX 75243
Manages R&D team in the area of CMOS, Nanotechnology and MEMS Keywords: Nanotechnology, MEMS, Sensors, Piezoelectrics, Transducers, High Voltage Isolation, High Voltage, Precision, Analog, P...
from Jan 2017
Foundry Technoloy, Senior Manager
101 Innovation Dr, San Jose, CA 95134
Managed engagement between Altera and Intel Custom Foundry
Led Intel Foundry technical and business evaluation. Responsibilities included leading the 14nm technical evaluation team, partic...
Aug 2010 — Mar 2014
Senior Manager, 3D Integration and Mems Technology Development
Santa Clara, CA
Apr 2006 — Oct 2010
Manufacturing Operations Director
Staffed and managed manufacturing organization. Responsible for creating and managing manufacturing budget. Developed and validated yield, wafer, assembly, and reticle cost models and manage...
Dec 2004 — Apr 2006
Senior Manager, Process Technology
3401 Hillview Ave, Palo Alto, CA 94304
Technical leader and manager for 90nm and 65 nm mixed signal CMOS technology. Foundry and Design Team interface. Responsible for defining and negotiating technology requirements and features...
Sep 2001 — Dec 2004
Soi Process Integration Lead and Manager
New York, NY
Led 130nm SOI CMOS development and release to production of several high performance microprocessors and SRAM
Aug 1997 — Sep 2001
Senior Engineer
Santa Clara, CA
Process development of 0.25 micron CMOS technology.
Sep 1996 — Aug 1997
Member of Reserach Staff
Development and characterization of a 0.5 um CMOS SOI process, a 1 micron radiation tolerant process, a bulk 0.5 um CMOS process and novel SOI device structures such as the first “gate-all-a...
Sep 1989 — Sep 1992
Education
Occupations
Executive
Director
Senior Director
Health Specialist
Ultrasonographer
Operations Manager
Senior Manager
Sonographer
Medical Sonographers
Skills
Cmos
Silicon
Semiconductors
Mixed Signal
Ic
Microprocessors
Process Integration
Metrology
Reliability
Electronics
Mems
Processors
Characterization
Yield
Technology Development
Analog
Engineering Management
R&D
Integrated Circuits
Strategy
Foundry Management
Technological Innovation