Peter Hu

Lead System Level Product Engineer

Peter Hu is a qualified professional, working in Cadence Design Systems main office of which is in 1300. as a Lead System Level Product Engineer since 2018. Peter has earned professional experience in more than eight positions at different companies. Peter Hu went to the Stanford University and was studying there from 2019. Sunnyvale, California is the city, where this expert was known to be settled. This professional's phone and email are easily accessed through this website by request.
Name variants:
Petr Hu, Pete Hu, Petie Hu, Petey Hu
Last updated Jun 11, 2024

Contact Information

Last Update
Jul 14, 2022
Email
cq**@yahoo.com
Location
Sunnyvale, CA

Workplace

Cadence Design Systems
Lead System Level Product Engineer

San Jose, CA

Industry

Computer Software, Prepackaged Software, Dev Computer-Aided Design Software & Related Services, Develops Computer-Aided Design Software & Related Services, Software Development, Software Publishers

Work History

Lead System Level Product Engineer

2655 Seely Ave, San Jose, CA 95134
from Oct 2018

Product Engineer

500 Oracle Pkwy, California
Jul 2016 — Oct 2018

Eda Engineer Intern

5555 northeast Moore Ct, Hillsboro, OR 97124
Implemented Lattice’s CAD verification flow for TSMC and UMC foundry technologies. Identified a bottleneck in the QA process. Resolved it by automating the post-process step for model QA t...
Jun 2015 — Sep 2015

Principal Engineer

1 Technology Dr, Milpitas, CA 95035
from Mar 2014

Intel's Ultimate Engineering Experience Intern

Santa Clara, CA
Built applications for a wide range of target platforms, from web to microcontrollers to quadcopter robots. Co-led a team in of five in Arduino microcontroller project coding competition, wo...
Jun 2013 — Aug 2013

Industry Coordinator

455 Hoes Ln, Piscataway, NJ 08854
Co-wrote business proposal and secured over $4000 in sponsorship. Initiated and continued to strengthen existing partnership with AT&T and Intel. Organized industry nights and invited rep...
Sep 2012 — Aug 2015

Director of R and D Engineering

Research and develop Inverse Lithography Technology for Computational Lithography including Resolution Enhancement Techniques in deep sub-wavelength lithography. Design and formulate mathe...
Dec 2004 — Mar 2014

Architect

500 Oracle Pkwy, California
Oracle Financial Intelligence, Business Intelligence Applications / Design / Architecture. Design and project lead for Financial Intelligence component of Oracle Daily Business Intelligence ...
Jul 1999 — Dec 2004

Education

Occupations

Engineer
Head Engineer
Executive
Director
Engineering Manager
Operations Manager

Skills

Algorithms
Databases
Lithography
Numerical Analysis
Business Intelligence
Sql
C
Python
Integration
Eda
Perl
Pl/Sql
Software Development
Teamwork
Team Building
Team Leadership
Microsoft Office
Design For Manufacturing
Debugging
Hardware Diagnostics
Data Analysis
Npi
Manufacturing Operations
Matlab
Cadence Virtuoso
Troubleshooting
Embedded Systems
Lean Manufacturing
Networking
C++
Unix
Labview
Eda Tools
Altera Quartus
Hspice
Pspice
Irsim
Pcb Design
Cliosoft Sos
Modelsim
Linux
Ni Labview
Microsoft Word
Microsoft Excel
Microsoft Powerpoint
Microsoft Outlook
Product Development
Visual Basic For Applications
Oracle Agile Plm
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