Nupur Shah
Senior Director, Strategic Software and Boards Planning, Programmable Solutions Group
Nupur Shah is a high-level professional, that works in Intel Corporation main office of which is in 1286. on the position of Senior Director, Strategic Software and Boards Planning, Programmable Solutions Group since 2018. This person has earned professional experience in more than seven positions at various companies. Nupur Shah went to the Massachusetts Institute of Technology and received education from 1995 to 1996. San Francisco, California is the area, where this expert was known to be living. Nupur Shah's e-mail and phone can be accessed through this website on demand.
Name variants:
Nupur Shah
Last updated Jun 10, 2024
Contact Information
Workplace
Senior Director, Strategic Software and Boards Planning, Programmable Solutions Group
Santa Clara, CA
Industry
Semiconductors
Colleagues
Work History
Senior Director, Strategic Software and Boards Planning, Programmable Solutions Group
Santa Clara, CA
from Sep 2018
Director of Engineering
5201 Great America Pkwy SUITE 422, Santa Clara, CA 95054
Jul 2015 — Aug 2018
Senior Director and Director, Applications
3250 Olcott St, Santa Clara, CA 95054
Grew and led a world-wide team of experienced and highly skilled Application engineers focused on reference design development and delivery, design services, and customer support focused on ...
Aug 2010 — Mar 2015
Senior Manager
2100 Logic Dr, San Jose, CA 95124
Software Quality and Benchmarking Team. Responsible for a team of engineers focused on driving a consistent benchmarking methodology in software development. This includes development and ma...
Oct 2006 — Aug 2010
Senior Manager, Xilinx India
2100 Logic Dr, San Jose, CA 95124
Xilinx India Site Establishment and IP/DSV Engineering Management. Responsible for establishing the first Xilinx engineering site based out of India. Temporarily relocated to India for initi...
Jul 2004 — Sep 2006
Manager, Ip Development
2100 Logic Dr, San Jose, CA 95124
Connectivity IP Development and Management. Responsible for management and development of RapidIO, Hypertransport and PCI Express Link Layer connectivity IP. Engaged with marketing to define...
Jan 2000 — Jun 2004
Ip Development Engineer and Manager
2100 Logic Dr, San Jose, CA 95124
PCI IP Development and Project Management. Design, verification and implementation of several Xilinx PCI based products including PCI 32-bit Slave, PCI 64/66 Master/Slave and the PCI 64/66 P...
Jul 1996 — Dec 1999
Education
1995 — 1996
1991 — 1995
Occupations
Executive
Senior Director
Director
Senior Manager
Operations Manager
Skills
Fpga
Embedded Systems
Eda
Verilog
Asic
Debugging
Xilinx
Semiconductors
Soc
Functional Verification
Field Programmable Gate Arrays
Ic
Rtl Design
Vlsi
Simulations
Hardware
Static Timing Analysis
Integrated Circuit Design
Cvs
Tcl
Processors
Systemverilog
Application Specific Integrated Circuits
Technical Leadership
System on A Chip
Software Defined Networking
Virtualization
Networking
Management
Software Development
Cross Functional Team Leadership
Software Project Management
Multi Site Team Management
Microcontrollers
Integrated Circuits
Hands on Technical Leadership
Distributed Systems