Michael Anfang is a qualified professional, that works in Facebook main office of which is in 1067. as a Senior Fpga Engineer from 2019. This person gained professional experience in more than 11 positions at various companies. Michael Anfang went to the Cedarville University and was studying there from 2003 to 2007. Chicago, Illinois is the area, where this expert was known to live. This person's phone number and email are accessed through SoftwareOfficial on demand.
Name variants:
Mikael Anfang,
Mychael Anfang,
Mike Anfang,
Mikey Anfang,
Mick Anfang,
Mickey Anfang,
Micky Anfang,
Michl Anfang,
Mischa Anfang
Last updated May 30, 2024
Contact Information
Workplace
Colleagues
Work History
Senior Fpga Engineer
1 Hacker Way, Menlo Park, CA
Working with a forward-looking group at Facebook Reality Labs to implement FPGA-based solutions for next-gen Virtual and Augmented Reality applications.
from Nov 2019
Senior Fpga Design Engineer and Consultant
21512 northeast 373Rd St, Yacolt, WA 98675
Founder of an FPGA design and consulting company, working on all phases of FPGA design.
DSP and IP integration, AXI and custom IP
High speed designs with multiple clock domains
Testing a...
from Jan 2017
Senior Fpga Engineer
3740 Industrial Ave, Rolling Meadows, IL 60008
Teamed with Epiq bring to market the smallest of modular, custom software defined radios, in mPCIe and M.2 form factors. Epiq had single-digit employees when I joined, and has since scaled ...
Nov 2012 — Dec 2016
Engineering Technical Lead
Developing test platforms for automotive electronics
Reverse engineering electronics
Managing Bluetooth helpdesk and PODS airbag program
Apr 2011 — Oct 2012
Engineering Technical Lead
615 east Crescent Ave, Ramsey, NJ 07446
I joined Model to lead their efforts in improving their techniques and tools to repair automotive electronics.
Developed test platforms and tools for automotive electronics - Clusters and ...
Apr 2011 — Oct 2012
FPGA Design Engineer
FPGA implementations of aviation communication protocols for test sets. ~50k Logic elements @ 80 Mhz.
SIF, Mode 4, HPI, FPGA/CPLD communication bus
Implemented Mode 5 core in VHDL
Implement...
2008 — Mar 2011
Fpga Design Engineer
New Jersey
FPGA design and implementation of aviation communication protocols for ramp test sets. Upgraded TS-4850 test set to meet AIMS verification standard for Mode 5 IFF based on a Matlab model Dev...
2008 — Mar 2011
Owner
IT support and custom computer builds for consumers and local small business.
2008 — 2009
Project Manager
1 Terminal Dr, Plainview, NY 11803
Managed system construction and integration of MOCVD systems with customized hardware and software flows for customers
Developed and customized CAD drawings
Managed software version contr...
2007 — 2008
Chief Executive Officer and Chicken Engineering Officer
21512 northeast 373Rd St, Yacolt, WA 98675
Education
2003 — 2007
Occupations
Philanthrope
Engineer
Skills
VHDL
C++
Python
Linux
Analysis
FPGA
Testing
Electronics
Fpga
Vhdl
Embedded Systems
Embedded Software
Electrical Engineering
Debugging
Xilinx
Pcb Design
I2C
Chickens