Joydip Das

Senior Physical Design Engineer I

Joydip Das is a skilled professional, who works in Silicon Integration Initiative, Inc main office of which is in 1. on the position of Chair of Special Interest Group on Ml and Eda since 2019. This expert has earned professional experience in more than five positions at different companies. Joydip Das went to the The University of British Columbia and was studying there from 2008 to 2012. Santa Clara, California is the area, where this expert was lastly known to be situated. Joydip Das's contacts are easily accessed through SoftwareOfficial by request.
Name variants:
Joydip Das
Last updated May 29, 2024

Contact Information

Last Update
Jul 9, 2022
Email
jo**@gmail.com, jo**@gmail.com, jo**@achronix.com
Location
Santa Clara, CA
Company
Silicon Integration Initiative, Inc.

Workplace

Chair of Special Interest Group on Ml and Eda

Work History

Chair of Special Interest Group on Ml and Eda

9111 Jollyville Rd SUITE 250, Austin, TX 78759
Special Interest Group (SIG) on Best practices of Machine Learning from EDA aspects. (http://www.si2.org/). The SIG aims to find out the best practices of AI/ML usage in regards to the EDA t...
from Aug 2019

Senior Physical Design Engineer I

Austin, TX
from Oct 2016

Senior Hardware Engineer

2903 Bunker Hill Ln, Santa Clara, CA 95054
Working with the Core Technology group at this startup FPGA company. My responsibilities include ASIC verification, bringup and testing. The FPGA chip has been fabricated using 22nm technolo...
Jun 2012 — Mar 2013

Research Assistant and Ph D Candidate

Worked as a Research Assistant in the project: “Analytical Model for FPGA Architecture Development”. Developed a set of simple equations that would substantially speed up the design process ...
Jun 2008 — May 2012

Research Assistant

104 University Cir, Lafayette, LA
Worked as a Research Assistant. Designed and implemented low-energy adders and multipliers in 120 nm technology using adiabatic circuit technique. Also designed VLSI architecture for Detecti...
2004 — 2006

Occupations

Engineer
Project Engineer
Executive
Chairperson
Government Official
State Inspector General
Counselor
Engineering Specialist
Chief Executive
State Inspector
Inspector
Advisor

Skills

Fpga
Simulations
Vlsi
Asic
C
Perl
Computer Architecture
Verilog
C++
Linux
Python
Matlab
Vhdl
Cadence Virtuoso
Field Programmable Gate Arrays
Fortran
Algorithms
Cadence
Static Timing Analysis
Low Power Design
Data Analysis
Simulation
Artificial Neural Networks
Cadence Framework
Physical Design
Machine Learning
Computer Aided Design
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