Jason Corley is a skilled expert, who works in Karl Storz Imaging main office of which is in 691. as a Fpga Iv from 2015. Jason Corley has earned professional experience in more than nine positions at various companies. Jason Corley went to the The Hong Kong University of Science and Technology and received education from 2006 to 2008. Clinton, Mississippi is the city, where this expert was known to live. This expert's contacts are accessed through SoftwareOfficial on demand.
Name variants:
Jayson Corley,
Jay Corley
Last updated May 24, 2024
Contact Information
Last Update
Jul 8, 2022
Email
ja**@karlstorz.com, ja**@yahoo.com, ja**@webtv.net
Location
Clinton, MS
Company
Workplace
Colleagues
Work History
Fpga Iv
1 south Los Carneros Rd, Goleta, CA 93117
Verilog, SystemVerilog design for medical video
from Jun 1, 2015
Senior Design Engineer
2071 Lemoine Ave SUITE 302, Fort Lee, NJ 07024
Designed a Gbps wireless modem in an Altera Stratix V FPGA. Datapath ran at 288MHz and 575MHz, and control was implemented in a NIOS embedded CPU running at 125MHz.
Designed and tested DAC...
Sep 2014 — Jun 2015
Applications Engineer
Supported engineers in Taiwan and China with technical issues on VDSL2 products
Worked with Infineon’s marketing team to present products to customers
Aug 2004 — Mar 2006
Senior Design Engineer
3901 Genesee St SUITE 300, Buffalo, NY 14225
Redesigned the MAC layer of a proprietary wireless systems to increase the number of simultaneous subscribers 20 times, while still being backward compatible. Changed the reservation request...
Jun 2002 — Aug 2004
Senior Design Engineer
Maintained existing MAC-layer designs on a Xilinx FPGA using VHDL and Verilog.
Led a small team working on the next-generation MAC
Mar 2000 — Jun 2001
Fpga and Board Design Engineer
New York, NY
Designed and tested a PCB and several CPLD’s working in a low-noise environment
1999 — 1999
Design Engineer
Designed filters, timing recovery, and other modules for a VDSL modem using an Altera CPLD and other devices
Verified VHDL design against the C system model and tested designs in the lab
...
Mar 1997 — Nov 1998
Intern To Engineer
Designed a PCB and Xilinx XC4013 FPGA in VHDL
Dec 1994 — Nov 1996
Education
2001 — 2001
1990 — 1995
Occupations
Engineer
Senior Design Engineer
Head Engineer
Engineering Manager
Skills
Verilog
Fpga
Embedded Systems
Xilinx
Signal Processing
Vhdl
Altera
Asic
Systemverilog
Ic
Integrated Circuit Design
Field Programmable Gate Arrays
Application Specific Integrated Circuits
Electrical Engineering
Zynq
Modelsim
Simulations
Wireless
Semiconductors
Ldpc
Hardware