Geethika Sabbineni is a eficient professional, working in Intel Corporation main office of which is in 1286. as a Big Core Structural Design Engineer since 2018. Geethika has earned professional experience in more than five positions at different companies. Geethika Sabbineni went to the Ira A. Fulton Schools of Engineering at Arizona State University and got education there from 2015 to 2017. Peoria, Illinois is the city, where this expert was known to be located. The person's email address and phone are accessed through this website on demand.
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Geethika Sabbineni
Last updated Jun 16, 2024
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Work History
Big Core Structural Design Engineer
Santa Clara, CA
Performed timing analysis (STA) on ROMs for multiple projects.
Debugged relevant issues and fixed them using transistor sizing, logic optimization, layout and floorplan optimization.
Perf...
from Jul 30, 2018
Asic Design Intern
544 Monterey Rd, Pacifica, CA 94044
Timing closure for DDR3-DRAM Controller
Apr 2018 — Jul 2018
Memory Design Co-Op Engineer
ARM, Austin, TX (Intern, Standard cell) May 2017-Aug 2017 Developed layouts for ASAP7nm PDK for both 7.5-T and 9-T architectures using Euler theory. Gained experience Design Automation by wr...
Jan 2017 — Aug 2017
Disability Resource Center, Asu
Formatted the text files and pictures into a readable format that is accessible for people with vision problems.
Apr 2016 — Dec 2016
Intern
Worked on analyzing the overall power plant. Studied the automated control system circuits that control various operations of the power plant.
Jun 2013 — Jul 2013
Education
2015 — 2017
2009 — 2011
1998 — 2007
Occupations
Engineer
Project Engineer
Apprentice
Accountant
Controller
Engineering Specialist
Student Worker
Skills
Customer Service
Microsoft Excel
Microsoft Word
Powerpoint
Microsoft Office
Management
Verilog
C
Matlab
C++
Cadence Virtuoso
Linux
Perl
Digital Circuit Design
Pspice
Ltspice
Analog Circuit Design
System Verification
Logic Design
Cadence Icfb
Vhdl
Programming
Java
System Verilog
Mips Instruction Set
Layout Design
Analog Circuits
Perc
Xps
Standard Cell
Cadence Spectre
Field Programmable Gate Arrays
Rtl Design
Vlsi
Integrated Circuit Design
Application Specific Integrated Circuits
Static Timing Analysis
Physical Design
System on A Chip
Eda