David H Culley is a high-skilled professional, who works in Maxlinear main office of which is in 320. on the position of Senior Principal Asic Design Engineer since 2020. This person has earned professional experience in more than six positions at different companies. David H Culley went to the Simon Fraser University and received education there from 2000 to 2007. San Marcos, California is the area, where this professional was known to live. This professional's phone number and email can be accessed through SoftwareOfficial on demand.
Name variants:
Daved Culley,
Dayvid Culley,
Dave Culley,
Davey Culley,
Davie Culley,
Davy Culley
Last updated Apr 29, 2024
Contact Information
Workplace
Senior Principal Asic Design Engineer
Carlsbad, CA
Industry
Semiconductors, Mfg Semiconductors & Related Devices, Mfg Semiconductors and Related Devices, Mfg Semiconductors/Related Devices
Colleagues
Work History
Senior Principal Asic Design Engineer
2051 Palomar Airport Rd SUITE 100, Carlsbad, CA 92011
from Jun 2020
Principal Design Engineer
380 Stevens Ave SUITE 206, Solana Beach, CA 92075
FPGA implementation of cutting edge Video Processing IP for product development, All digital clock recovery, Xilinx & Altera FPGA integration.
from Feb 1, 2013
Principal Engineer - Soc
50 Old Webster Rd, Oxford, MA 01540
Leader and technical go-to person for FPGA based implementation of 10Gbps and 100Gbps optical telecom platforms. - Develop and maintain proprietary Communications IP including OTN, SONET/SDH...
Jan 2011 — Feb 2013
Principal Engineer
Fremont, CA
Mentor and lead teams of junior digital engineers in the implementation and verification of FPGA based 10Gbps optical network access projects. Our team was spun off after product success to ...
Oct 2008 — Jan 2011
Product Engineer
1380 Bordeaux Dr, Sunnyvale, CA 94089
For this contract position, I was responsible for characterizing new analog IP in a 45nm test chip. - This position involved designing, implementing and executing tests of analog and digital...
Mar 2008 — Aug 2008
Leader - Product Development
1380 Bordeaux Dr, Sunnyvale, CA 94089
Responsible for the complete development cycle of 4 communications and SOC chips (three of which were released to production without any design revisions required). - Effectively led teams o...
Sep 1995 — Mar 2007
Education
Occupations
Engineer
Project Engineer
Professor
School Principal
Engineering Specialist
School Administrator
Educational Manager
Skills
Asic
Verilog
Fpga
Soc
Vhdl
Integrated Circuit Design
Ic
Tcl
Ethernet
System Architecture
Embedded Systems
Product Development
Telecommunications
Product Management
Sdh
Otn
Semiconductors
System on A Chip
Technical Leadership
Analog
Application Specific Integrated Circuits
Field Programmable Gate Arrays
Integrated Circuits
Rtl Verification
Project Management
Technical Documentation
Digital Design