Alexander Shternshain is a high-skilled professional, that works in Intel Corporation main office of which is in 1286. as a Senior Hw and Rtl Design Engineer from 2016. Alexander has earned professional experience in more than 11 positions at different companies. Alexander Shternshain went to the Technion - Israel Institute of Technology and was studying there from 1990 to 1994. San Francisco, California is the area, where this person was lastly known to be living. Their e-mail and phone are accessed through this website by request.
Name variants:
Aleksander Shternshain,
Alixander Shternshain,
Alekzander Shternshain,
Alexzander Shternshain,
Al Shternshain,
Alex Shternshain,
Alec Shternshain,
Aleck Shternshain,
Lex Shternshain,
Sandy Shternshain,
Sander Shternshain,
Xander Shternshain
Last updated Jan 17, 2024
Contact Information
Last Update
Jul 1, 2022
Email
sh**@hotmail.com, al**@intel.com
Location
San Francisco, CA
Company
Workplace
Colleagues
Work History
Senior Hw and Rtl Design Engineer
Santa Clara, CA
HW/RTL design engineer at Intel Corporation
Jan 1, 2016 — Jul 2018
Founder and Chief Executive Officer
Providing ASIC design services to leading semiconductors companies. Current project: Cadence DNA-100 Always open for new consulting opportunities.
from Jul 2018
Senior Staff Engineer
San Diego, CA
Wireless Modem design for latest LTE technologies.
May 2014 — Jan 2016
Digital Ic Design Engineer
1154 Sonora Ct, Sunnyvale, CA 94086
Architecture, design and verification of various SoC/DSP blocks for Power Amplifier linearization applications.
Jan 2012 — May 2014
Mts Design Engineer
2485 Augustine Dr, Santa Clara, CA 95054
Designed, implemented and integrated various digital blocks for PLLs, DLLs and Clock Recovery circuits for use in latest generation of AMD products.
Performed RTL design, synthesis, timing...
Feb 2009 — Nov 2011
Senior Engineer
High-level design of DSP blocks, generating technical documentation, RTL design and verification, formal verification and timing closure.
Jul 2007 — May 2008
Design Contractor
Working on the latest generation of SERDES, PLL and PCI-Express products using 65nm technology. - Job responsibilities included RTL design & validation, digital/analog integration, synthesis...
Jan 2007 — Jul 2007
Senior Engineer
1380 Bordeaux Dr, Sunnyvale, CA 94089
Led a design team of 4 engineers, implementing a PCI-Express physical interface in a mixed-signal 90nm ASIC.
Responsible for ASIC definitions, floor planning, digital blocks design and syn...
Apr 2004 — Sep 2006
Senior Engineer
Santa Clara, CA
Designed various Digital Signal Processing blocks for a Gigabit Ethernet chip in RTL.
Validated the design using NCSim RTL simulator and C-model simulations, both on block level and chip l...
Jun 2002 — Aug 2003
Senior Engineer
San Diego, CA
Led the RTL design of a TDMA hardware core, implemented on an Altera FPGA. The core included Transmit/Receive digital signal processing and interfaces with the host DSP and ARM processors, b...
Mar 1998 — Jun 2002
Engineer
Santa Clara, CA
Performed a wide range of tasks:
Engineering Intern (93-94)
Circuit Designer (94-96)
Production Engineer (96-97)
System Validation team lead (97-98)
Mar 1992 — Mar 1998
Education
1990 — 1994
Occupations
Executive
Chief Executive Officer
Founder
Engineer
Project Engineer
Corporate Executive
Chief Executive
Founding Member
Engineering Specialist
Skills
Asic
Rtl Design
Verilog
Static Timing Analysis
Fpga
Timing Closure
Debugging
Hardware Architecture
Digital Signal Processors
Semiconductors
Tcl
Vlsi
Formal Verification
Primetime
Modelsim
Mixed Signal
Application Specific Integrated Circuits
Ic
Ncsim
Altera
Pcie
Logic Synthesis
Xilinx
Logic Design
Synopsys Tools
Serdes
Field Programmable Gate Arrays
Vhdl
Digital Design
Hardware Design
Rtl Coding
Wireless
Soc